A simple and cost-effective way of forming capacitors for integrated circuits is to use side-by-side runners of interconnect metal. To enhance capacitor area the runners may be interdigitated. See U.S. Pat. No. 6,383,858, issued May 7, 2002, and incorporated herein by reference. Since the capacitor dielectric may be formed by the interlevel dielectric of the integrated circuit (IC) these passive devices can be formed with no additional IC processing steps. Capacitance may be further increased by stacking interdigitated structures in a multi-level configuration. (See the patent referenced above).
Capacitors of this type may be integrated with active devices in a conventional integrated circuit, or may comprise portions of integrated passive devices (IPDs), where the capacitors are combined with inductors, resistors etc., to form a passive device network. IPDs typically are formed on high resistivity substrates and may have no active elements. In either case, capacitors are commonly used in pairs or other groupings.
For some IC applications, paired capacitors are required to have equivalent electrical characteristics. The straightforward method to obtain matched capacitor pairs is to form them with identical structures using the same processing steps. While that approach is largely successful, precise matching of capacitors, even when formed side-by-side on a substrate wafer, may not result. This is often due to dimensional variations in the runners, or the dielectric. These variations occur in both the thickness dimension, for example, the interlevel dielectric thickness, and in the lateral dimension, and are typically attributed to processing conditions. The thickness dimension is usually thought of as the z-direction, with the lateral dimension(s) corresponding to the x-y plane of the substrate wafer. Capacitor pair mismatch commonly occurs due to localized thickness variations in the metal runners from one capacitor structure to another.